Re: [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
From: Christian Hewitt <hidden>
Date: 2025-08-25 07:59:04
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On 25 Aug 2025, at 10:51 am, Anand Moon [off-list ref] wrote: As per S905 and S905X datasheet add missing cache information to the Amlogic GXBB and GXL SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness.
Hello Anand, I’m wondering if we are “enabling caching” in these patches (could be a significant gain, as per text) or we are “optimising caching” meaning the kernel currently assumes generic/safe defaults so having accurate descriptions in dt allows better efficiency (marginal gain)? Stats are also subjective to the workload used, but do you have any kind of before/after benchmarks? (for any of the SoCs in the patchset) Christian
quoted hunk ↗ jump to hunk
Signed-off-by: Anand Moon <redacted> --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+)diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 7d99ca44e660..c1d8e81d95cb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi@@ -95,6 +95,12 @@ cpu0: cpu@0 {compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>;@@ -105,6 +111,12 @@ cpu1: cpu@1 {compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>;@@ -115,6 +127,12 @@ cpu2: cpu@2 {compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>;@@ -125,6 +143,12 @@ cpu3: cpu@3 {compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>;@@ -134,6 +158,9 @@ l2: l2-cache0 {compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; -- 2.50.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic