[PATCH v2 4/4] arm64: dts: marvell: pxa1908: Add power domains
From: Duje Mihanović <duje@dujemihanovic.xyz>
Date: 2025-08-21 11:19:26
Also in:
linux-arm-kernel, linux-clk, linux-pm, lkml, phone-devel
Subsystem:
arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, arm/marvell pxa1908 soc support, the rest · Maintainers:
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Duje Mihanović, Linus Torvalds
Update the APMU clock controller's compatible to allow the new power domain driver to probe. Also add the first two power domain consumers: IOMMU (fixes probing) and framebuffer. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> --- v2: - Drop power controller node - &pd -> &apmu --- arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 1 + arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts
index 47a4f01a7077bfafe2cc50d0e59c37685ec9c2e9..d61922f326a4654a45ab4312ea512ac1b8b01c50 100644
--- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts
+++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts@@ -23,6 +23,7 @@ chosen { fb0: framebuffer@17177000 { compatible = "simple-framebuffer"; reg = <0 0x17177000 0 (480 * 800 * 4)>; + power-domains = <&apmu PXA1908_POWER_DOMAIN_DSI>; width = <480>; height = <800>; stride = <(480 * 4)>;
diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
index cf2b9109688ce560eec8a1397251ead68d78a239..ae85b90eeb408a8f4014ec7b60048ae1fd3d4044 100644
--- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi
+++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi@@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/marvell,pxa1908.h> +#include <dt-bindings/power/marvell,pxa1908-power.h> / { model = "Marvell Armada PXA1908";
@@ -79,6 +80,7 @@ smmu: iommu@c0010000 { #iommu-cells = <1>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&apmu PXA1908_POWER_DOMAIN_VPU>; status = "disabled"; };
@@ -291,9 +293,10 @@ sdh2: mmc@81000 { }; apmu: clock-controller@82800 { - compatible = "marvell,pxa1908-apmu"; + compatible = "marvell,pxa1908-apmu", "syscon"; reg = <0x82800 0x400>; #clock-cells = <1>; + #power-domain-cells = <1>; }; }; };
--
2.50.1