Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
From: Bjorn Andersson <andersson@kernel.org>
Date: 2025-08-12 03:45:14
Also in:
linux-arm-msm, linux-pm, lkml
On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Reviewed-by: Konrad Dybcio <redacted> Signed-off-by: Taniya Das <redacted> ---
DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
The missing clock-names in clock-controller@100000 predates this series.
Sorry for merging broken patches in the past, please fix that as well.
Regards,
Bjorn
quoted hunk ↗ jump to hunk
arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi@@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,qcs615-camcc.h> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h> #include <dt-bindings/clock/qcom,qcs615-gcc.h> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h> +#include <dt-bindings/clock/qcom,qcs615-videocc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h>@@ -1506,6 +1510,18 @@ data-pins { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0 0x05090000 0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>,@@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>,-- 2.34.1