On Sun, Jul 20, 2025 at 06:27:26PM -0500, Rob Herring wrote:

quoted

+description: |
+  FPGA-based I3C controller designed to interface with I3C and I2C peripherals,
+  implementing a subset of the I3C-basic specification. The IP core is tested
+  on arm, microblaze, and arm64 architectures.
+
+  https://analogdevicesinc.github.io/hdl/library/i3c_controller
+
+maintainers:
+  - Jorge Marques [off-list ref]
+
+properties:
+  compatible:
+    const: adi,i3c-master-v1

If you want to use version numbers, they need to correlate to something 
and you need to document what that is. I don't see anything in the above 
link about a version 1. Kind of feels like you just made it up.

I asked already at v4 to document the naming/versioning, which was a
result of one of previous discussions, in the binding description. :/

quoted

+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: The AXI interconnect clock, drives the register map.
+      - description: The I3C controller clock. AXI clock drives all logic if not provided.

Is that a description of how the h/w works? The controller clock input 
can literally be left disconnected? If 1 clock source drives both 
inputs, then the binding should reflect that.

This was explained in reply, but never made as proper explanation to the binding.

Jorge,
When you answer to a review about uncertain pieces like that, usually
outcome of the discussion must end up also in new patch - either in
commit msg or better in the binding itself. I also asked about this -
documenting the outcode - in v4.

Best regards,
Krzysztof