Hi Andrew,

On Di, 2025-05-24 at 19:44 -0300, Andrew Lunn wrote:

quoted

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 88c2657b50e6..b481097f08a4 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi

@@ -68,6 +68,8 @@ mdio: mdio {
              ethphy1: ethernet-phy@1 {
                      compatible = "ethernet-phy-ieee802.3-c22";
                      reg = <1>;
+                     reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+                     reset-assert-us = <30>;

Is there anything in the datasheet about needing a delay after the
reset? There is a DT property for this:

 reset-deassert-us:
   description:
     Delay after the reset was deasserted in microseconds. If
     this property is missing the delay will be skipped.

No, there is no need for a delay after the reset mentioned in the datasheet.
There is only the delay after the assert (i.E. the pulse width), that I
declared with the property reset-assert-us.

Anyway:

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

Thanks, and regards,
Christoph

   Andrew