Re: [PATCH net-next v3 06/14] net: ethernet: qualcomm: Initialize the PPE scheduler settings
From: Jie Luo <hidden>
Date: 2025-02-20 14:50:32
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linux-arm-msm, linux-doc, linux-hardening, lkml, netdev
On 2/11/2025 9:32 PM, Andrew Lunn wrote:
quoted
+/* Scheduler configuration for the assigning and releasing buffers for the + * packet passing through PPE, which is different per SoC. + */ +static const struct ppe_scheduler_bm_config ipq9574_ppe_sch_bm_config[] = { + {1, 0, 0, 0, 0}, + {1, 1, 0, 0, 0}, + {1, 0, 5, 0, 0}, + {1, 1, 5, 0, 0}, + {1, 0, 6, 0, 0}, + {1, 1, 6, 0, 0}, + {1, 0, 1, 0, 0}, + {1, 1, 1, 0, 0},Rather than add a comment what it is, add a comment what it means.
Sure, I will enhance the comment to describe the functionality for this table better.
It also looks like the first, 3 and 4 value are fixed, so do they even need to be in the table? And the second value flip-flops? Andrew
This array is defined to closely reflect the layout of the scheduler BM configuration table in the PPE hardware. The value at index 0 indicates whether the entry is valid or not. In this case (for IPQ9574), all the entries are marked as 'enabled', but for a different IPQ SoC, some of these entries may be marked as disabled (Note: the table structure is same for all IPQ SoCs that support PPE). The values at index 3 and 4 indicate whether there is any backup port configured for assigning these buffers, in the case when the primary port is down. This option is disabled by default by the hardware for this SoC and hence the values are marked '0'. The value at index 1 flip flops, because for the same port, we have two entries - one for ingress port buffer assignment (value 0) and one for egress port buffer release (value 1). The value at index 2 is the port number. As a general rule, we have tried to keep the data structure definition accurately mirror the hardware table design, for easier understanding and debug ability of the code. I will change the values of array index 0/1/3 to true/false to make it more readable, thanks.