Re: [PATCH] arm: clk: Add ETH switch clock description for vf610 SoC
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: 2025-02-19 12:06:38
Also in:
imx, linux-arm-kernel, linux-clk, lkml
On 19/02/2025 12:49, Lukasz Majewski wrote:
The NXP's vf610 soc is equipped with L2 switch IP block from More Than IP (MTIP) vendor. It requires special clock (VF610_CLK_ESW) to be operational. Signed-off-by: Lukasz Majewski <lukma@denx.de> --- drivers/clk/imx/clk-vf610.c | 1 + include/dt-bindings/clock/vf610-clock.h | 3 ++-
Bindings are a separate patch.
quoted hunk ↗ jump to hunk
2 files changed, 3 insertions(+), 1 deletion(-)diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index 9e11f1c7c397..405bf48a1d28 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c@@ -309,6 +309,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0)); clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1)); + clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8)); clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 373644e46747..95446f1bee16 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h@@ -197,6 +197,7 @@ #define VF610_CLK_TCON1 188 #define VF610_CLK_CAAM 189 #define VF610_CLK_CRC 190 -#define VF610_CLK_END 191 +#define VF610_CLK_ESW 191 +#define VF610_CLK_END 192
This defiine should not change. If you need to change it, means it is not an ABI. Just like for other cases, I suggest to drop the define in preparatory patch. Best regards, Krzysztof