On Tue, 03 Dec 2024 08:57:56 +0100, Janne Grunau wrote:

This series adds SPI controller and SPI NOR flash device nodes to the
man Apple silicon SoC dts files. Only the subset of used SPI controllers
is added. Five SPI controllers exists according to pmgr ADT data but the
commits only add controllers found in use on any of the devices. The
parameters for the missing nodes are guessable but there's no point in
adding them since no further M1 or M2 devices are expected.
Together with controller nodes the first SPI device is added. All Apple
silicon devices connect a SPI NOR flash to spi1. This holds Apple's 1st
stage bootloader, firmwares, platform and machine specific config data
and a writeable key-value store (nvram). Expose only the nvram as mtd
partition since it has use beyond exploring the content. Tools from
asahi-nvram [1] can modify the (default) boot configuration
(asahi-bless), read Bluetooth sync keys (asahi-btsync) and read and
write arbitrary keys (asahi-nvram).

[...]

Applied, thanks!

[1/5] arm64: dts: apple: t8103: Fix spi4 power domain sort order
      commit: 1f7af2931158a5e819ac71bcba91e961ac5ca3ea
[2/5] arm64: dts: apple: t8103: Add spi controller nodes
      commit: 556cd4bbb45bb5a73042c02b7e5c982112a6ed1f
[3/5] arm64: dts: apple: t8112: Add spi controller nodes
      commit: 0a6d561c7e46bf46b886af209e8ebedb6d500680
[4/5] arm64: dts: apple: t600x: Add spi controller nodes
      commit: d08e455a865c99a8050addf4dc001bcfdf1b7b8b
[5/5] arm64: dts: apple: Add SPI NOR nvram partition to all devices
      commit: 3febe9de5ca5267618675650871a626d0901f8cb

Best regards,
-- 
Sven Peter [off-list ref]