[PATCH 10/11] drm: meson: add CVBS support for S4
From: Ao Xu via B4 Relay <devnull+ao.xu.amlogic.com@kernel.org>
Date: 2025-01-10 05:39:56
Also in:
b4-sent, dri-devel, linux-amlogic, linux-arm-kernel, lkml
Subsystem:
drm drivers, drm drivers and misc gpu patches, drm drivers for amlogic socs, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Neil Armstrong, Linus Torvalds
From: Ao Xu <redacted> Add support for Composite Video Baseband Signal (CVBS) in the Meson encoder driver for the Amlogic S4 SoC. Signed-off-by: Ao Xu <redacted> --- drivers/gpu/drm/meson/meson_encoder_cvbs.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
index d1191de855d910f9845bf2d5aef336e391982ba2..45ed800173c1754b23fdc8b53e9487530bcae5a3 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c@@ -30,6 +30,10 @@ #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ +/* ANA VDAC Registers */ +#define ANACTRL_VDAC_CTRL0 0x2c0 /* 0xb0 offset in data sheet */ +#define ANACTRL_VDAC_CTRL1 0x2c4 /* 0xb1 offset in data sheet */ + struct meson_encoder_cvbs { struct drm_encoder encoder; struct drm_bridge bridge;
@@ -187,6 +191,9 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0x406802); + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0xc4); } }
@@ -201,6 +208,9 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge, if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_S4)) { + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL0, 0); + regmap_write(priv->hhi, ANACTRL_VDAC_CTRL1, 0); } else { regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
--
2.43.0