On Fri, 03 Jan 2025 15:31:33 +0800, Luo Jie wrote:

The CMN PLL clock controller in Qualcomm IPQ chipsets provides
the clocks to the networking hardware blocks that are internal
or external to the SoC, and to the GCC. This driver configures
the CMN PLL clock controller to enable the output clocks. The
networking blocks include the internal blocks such as PPE
(Packet Process Engine) and PCS blocks, and external hardware
such as Ethernet PHY or switch. The CMN PLL block also outputs
fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ
as sleep clock supplied to GCC.

[...]

Applied, thanks!

[2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
      commit: f81715a4c87c3b75ca2640bb61b6c66506061a64

Best regards,
-- 
Bjorn Andersson [off-list ref]