[PATCH v1 3/5] riscv: dts: starfive: jh7110-common: assign 24MHz clock-frequency to uart0
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SUPERSEDED
From: E Shattow <hidden>
Date: 2025-01-02 19:46:10
Also in:
linux-riscv, lkml
Subsystem:
risc-v architecture, starfive devicetrees, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing, Conor Dooley, Linus Torvalds
Status: Superseded by v3 (posted 2025-05-02). [go to v3]
Revision v1 (3 revisions archived).
Revisions (3)
- v1 current
- v2 [diff against previous]
- v3 [diff against previous]
Set uart0 clock-frequency for better compatibility with operating system and downstream boot loader SPL secondary program loader. Signed-off-by: E Shattow <redacted> --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 651f9a602226..bf2f0c34ad4e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi@@ -636,6 +636,7 @@ GPOEN_DISABLE, }; &uart0 { + clock-frequency = <24000000>; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay";
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2.45.2