在 10/28/2024 11:46 PM, Konrad Dybcio 写道:
On 26.10.2024 8:18 PM, Dmitry Baryshkov wrote:
quoted
On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote:
quoted
On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote:
quoted
On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote:
quoted
On 25.10.2024 5:07 AM, Qingqing Zhou wrote:
quoted
Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
to limit DMA address range to 36bit width to align with system
architecture.
Signed-off-by: Qingqing Zhou <redacted>
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You probably also want to mark it `dma-coherent` (see e.g.
x1e80100.dtsi)
Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't
marked as such.
I don't think I have any documentation on this, so.. one way to find out!
I don't have qcs615 at hand, so a purely theoretical question. But how
should it break if we mark it as dma-coherent, while it is not?
The board will hang rather quickly
Konrad
Thanks for review comments from Konrad and Dmitry!
QCS615 SMMU hardware supports IO-coherency after confirming with Qualcomm hardware team.
We also try to add "dma-coherent" for APPS SMMU node and test some SMMU clients, such as UFS and Ethernet, these SMMU clients work well on QCS615.
Do you advise and agree to add "dma-coherent" for SMMU node?