Hi Billy,

thanks for your patch!

On Wed, Aug 21, 2024 at 9:07 AM Billy Tsai [off-list ref] wrote:

In the 7th generation of the SoC from Aspeed, the control logic of the
GPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin’s
value, direction, interrupt type, and other settings.

Signed-off-by: Billy Tsai <redacted>

(...)

+static inline u32 field_get(u32 _mask, u32 _val)
+{
+       return (((_val) & (_mask)) >> (ffs(_mask) - 1));
+}
+
+static inline u32 field_prep(u32 _mask, u32 _val)
+{
+       return (((_val) << (ffs(_mask) - 1)) & (_mask));
+}

Can't you use FIELD_GET and FIELD_PREP from
<linux/bitfield.h> instead?

+static inline void ast_write_bits(void __iomem *addr, u32 mask, u32 val)
+{
+       iowrite32((ioread32(addr) & ~(mask)) | field_prep(mask, val), addr);
+}
+
+static inline void ast_clr_bits(void __iomem *addr, u32 mask)
+{
+       iowrite32((ioread32(addr) & ~(mask)), addr);
+}

This as a whole looks a bit like a reimplementation of regmap-mmio, can you
look into using that instead?

Yours,
Linus Walleij