[PATCH v4 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree

[PATCH v4 00/13] riscv: Add support for xtheadvector · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 02/13] dt-bindings: cpus: add a thead vlen register length property · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 04/13] riscv: Add thead and xtheadvector as a vendor extension · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 05/13] riscv: vector: Use vlenb from DT for thead · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 06/13] RISC-V: define the elements of the VCSR vector CSR · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 08/13] riscv: Add xtheadvector instruction definitions · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 09/13] riscv: vector: Support xtheadvector save/restore · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 10/13] riscv: hwprobe: Add thead vendor extension probing · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 12/13] selftests: riscv: Fix vector tests · Charlie Jenkins <hidden> · 2024-07-03
[PATCH v4 13/13] selftests: riscv: Support xtheadvector in vector tests · Charlie Jenkins <hidden> · 2024-07-03

STALE738d REVIEWED: 3 (3M)

From: Charlie Jenkins <hidden>
Date: 2024-07-03 05:57:02
Also in: linux-doc, linux-kselftest, linux-riscv, linux-sunxi, lkml
Subsystem: risc-v architecture, the rest · Maintainers: Paul Walmsley, Palmer Dabbelt, Albert Ou, Linus Torvalds

The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <redacted>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..6367112e614a 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi

@@ -27,7 +27,8 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

-- 
2.44.0

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