Re: [PATCH v6 1/2] clk: qcom: gcc-ipq6018: update sdcc max clock frequency
From: Robert Marko <hidden>
Date: 2024-06-22 14:36:23
Also in:
linux-arm-msm, linux-clk, lkml
On 20. 06. 2024. 17:01, Chukun Pan wrote:
quoted hunk ↗ jump to hunk
The mmc controller of the IPQ6018 does not support HS400 mode. So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). Signed-off-by: Chukun Pan <redacted> --- drivers/clk/qcom/gcc-ipq6018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 7e69de34c310..6c764e3e2665 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { F(96000000, P_GPLL2, 12, 0, 0), F(177777778, P_GPLL0, 4.5, 0, 0), F(192000000, P_GPLL2, 6, 0, 0), - F(384000000, P_GPLL2, 3, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0),
Hi, Are you sure that 200MHz is even valid of a frequency, cause all IPQ SoC-s use 192MHz for the HS200 mode instead. I would just drop the 384MHz frequency as datasheet clearly states that HS400 is not supported. Regards, Robert
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};