Re: [PATCH v2 2/6] dt-bindings: riscv: Add Zicclsm ISA extension description.
From: Conor Dooley <conor.dooley@microchip.com>
Date: 2024-06-14 08:07:13
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On Thu, Jun 13, 2024 at 03:16:11PM -0400, Jesse Taube wrote:
quoted hunk ↗ jump to hunk
Add description for Zicclsm ISA extension. Signed-off-by: Jesse Taube <redacted> --- V1 -> V2: - New patch --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+)diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cfed80ad5540..9f6aae1f5b65 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml@@ -317,6 +317,13 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicclsm + description: + The standard Zicclsm extension for misaligned support for all regular + load and store instructions (including scalar and vector) but not AMOs + or other specialized forms of memory access. Defined in the + RISC-V RVA Profiles Specification.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
+
- const: zicntr
description:
The standard Zicntr extension for base counters and timers, as
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