Re: [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller
From: Krzysztof Kozlowski <hidden>
Date: 2024-02-17 09:12:21
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linux-arm-kernel, linux-riscv, lkml
On 16/02/2024 01:08, Samuel Holland wrote:
From: Eric Lin <redacted> Add YAML DT binding documentation for the SiFive Private L2 Cache controller. Some functionality and the corresponding register bits were removed in the sifive,pl2cache1 version of the hardware, which creates the unusual situation where the newer hardware's compatible string is the fallback for the older one. Signed-off-by: Eric Lin <redacted> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v1: - Add back select: clause to binding - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 - Fix the order of the reg property declaration - Document the sifive,perfmon-counters property
This is no v1. Please implement entire feedback from previous v2, v3 or whatever it was and reference old posting or continue the numbering. Best regards, Krzysztof