Re: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2024-02-09 17:14:14
Also in:
linux-arm-kernel, linux-renesas-soc, linux-samsung-soc, linux-spi, lkml
Hi Tudor, On Thu, Feb 8, 2024 at 2:51 PM Tudor Ambarus [off-list ref] wrote:
There are instances of the same IP that are configured by the integrator with different FIFO depths. Introduce the fifo-depth property to allow such nodes to specify their FIFO depth. We haven't seen SPI IPs with different FIFO depths for RX and TX, thus introduce a single property.
Ha...
Current documentation for the Clock-Synchronized Serial Interface with
FIFO (MSIOF) on e.g. R-Car Gen2 and later states:
FIFO capacity: 32 bits × 64 stages for transmission and 32 bits ×
256 stages for reception
Initially (many years ago), there was some doubt about the validity
of these values (older variants on SH supported 64/64), hence
drivers/spi/spi-sh-msiof.c still has
.tx_fifo_size = 64,
.rx_fifo_size = 64,
Probably we should test and revisit this...
quoted hunk ↗ jump to hunk
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml@@ -69,6 +69,11 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the data FIFO in bytes.
I think it is prudent to consider the asymmetric case, too.
Whether that should be just two properties ("rx-fifo-depth" and
"tx-fifo-depth"), or also a third "fifo-depth", I defer to the DT
maintainers...
+
num-cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds