On 1/18/24 01:23, Konrad Dybcio wrote:

On 1/17/24 18:34, Sibi Sankar wrote:

quoted

Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
controller.

Signed-off-by: Sibi Sankar <redacted>
---

Hey Konrad,

Thanks for taking time to review the series.

[...]

quoted

+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mailbox@17430000 {
+        compatible = "qcom,x1e80100-cpucp-mbox", "qcom,cpucp-mbox";
+        reg = <0x17430000 0x10000>, <0x18830000 0x300>;

These reg spaces are quite far apart.. On 7280-8550, a similar
mailbox exists, although it's dubbed RIMPS-mbox instead. In
that case, I separated the mbox into tx (via
qcom-apcs-ipc-mailbox.c) and rx (with a simple driver). Still
haven't pushed or posted that anywhere, I'd need to access
another machine..

On (some of) these SoCs, one of the channels (rx[1], iirc?) clearly
bleeds into the CPUFREQ_HW/OSM register region, which gives an
impression of misrepresenting the hardware. X1E doesn't have a
node for cpufreq_hw defined, so I can't tell whether it's also the
case here.

I am aware of ^^ discussion and the X1E doesn't have this problem.
Both the regions described are only used for mailbox communication.
X1E uses the scmi perf protocol for cpu dvfs.

-Sibi

Konrad