Hi Krzysztof,

As explained in my [PATCH v22 4/8] dt-bindings: soc: nuvoton: add
binding for clock and reset registers mail.

In the NPCM8XX SoC, the reset and the clock register modules are
scrambled in the same memory register region.
The NPCM8XX Clock driver is still in the upstream process (for a long
time) but the NPCM8XX reset driver is already upstreamed.

On Wed, 10 Jan 2024 at 22:59, Krzysztof Kozlowski
[off-list ref] wrote:

On 08/01/2024 14:54, Tomer Maimon wrote:

quoted

Replace reg with syscon property since the clock registers handle the
reset registers as well.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../bindings/clock/nuvoton,npcm845-clk.yaml   | 22 +++++++++----------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
index 0b642bfce292..c6bf05c163b4 100644
--- a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml

@@ -18,8 +18,9 @@ properties:
     enum:
       - nuvoton,npcm845-clk

-  reg:
-    maxItems: 1
+  nuvoton,sysclk:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to access clock registers.

NAK. Not explained, not justified, not reasonable, breaking ABI.

Should I explain more in the commit message or/and the nuvoton,sysclk property?

Best regards,
Krzysztof

Best regards,

Tomer