[PATCH v3 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe
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STALE1148d
SUPERSEDED
From: Krishna chaitanya chundru <hidden>
Date: 2023-08-21 14:15:59
Also in:
linux-arm-msm, linux-pci, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
Revision v3 of 7 in this series.
Revisions (7)
PCIe needs to choose the appropriate performance state of RPMH power domain based up on the PCIe gen speed. So let's add the OPP table support to specify RPMH performance states. Use opp-level for the PCIe gen speed for easier use. Signed-off-by: Krishna chaitanya chundru <redacted> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 595533a..3af0cf9 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi@@ -1803,7 +1803,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie0_phy: phy@1c06000 {
@@ -1915,7 +1936,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-level = <1>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-2 { + opp-level = <2>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-3 { + opp-level = <3>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-4 { + opp-level = <4>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; pcie1_phy: phy@1c0f000 {
--
2.7.4