On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:

 	 
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 On Fri, Jun 2, 2023 at 5:04 PM Yong Wu [off-list ref] wrote:

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From: "Chengci.Xu" <redacted>

MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the

other

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is for vpp. and 1 INFRA IOMMU.

Signed-off-by: Chengci.Xu <redacted>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <

angelogioacchino.delregno@collabora.com>

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---
 drivers/iommu/mtk_iommu.c | 49

+++++++++++++++++++++++++++++++++++++++

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 1 file changed, 49 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c89cf894a4d..5c66af0c45a8 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c

@@ -170,6 +170,7 @@ enum mtk_iommu_plat {
        M4U_MT8173,
        M4U_MT8183,
        M4U_MT8186,
+       M4U_MT8188,
        M4U_MT8192,
        M4U_MT8195,
        M4U_MT8365,

@@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data

mt8186_data_mm = {

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        .iova_region_larb_msk = mt8186_larb_region_msk,
 };

+static const struct mtk_iommu_plat_data mt8188_data_infra = {
+       .m4u_plat         = M4U_MT8188,
+       .flags            = WR_THROT_EN | DCM_DISABLE |

STD_AXI_MODE | PM_CLK_AO |

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+                           MTK_IOMMU_TYPE_INFRA |

IFA_IOMMU_PCIE_SUPPORT |

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+                           PGTABLE_PA_35_EN |

CFG_IFA_MASTER_IN_ATF,

FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
string,
but set via a DT property. The IOMMU controls are secured by
firmware.
It is not a property intrinsically tied to the hardware.

The flag CFG_IFA_MASTER_IN_ATF means the registers which enable/disable
iommu are in the secure world. If the master like pcie want to enable
iommu, we have to enter secure world to configure it. It should be HW
intrinsical, right?

If on some other project there is no such security requirement and
the
IOMMU is opened up to non-secure world, and ATF not even having
support
for the SMC call, this becomes unusable and hard to rectify without
introducing a new compatible string.

ChenYu

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+       .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
+       .banks_num        = 1,
+       .banks_enable     = {true},
+       .iova_region      = single_domain,
+       .iova_region_nr   = ARRAY_SIZE(single_domain),
+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vdo = {
+       .m4u_plat       = M4U_MT8188,
+       .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS |

OUT_ORDER_WR_EN |

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+                         WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE

|

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+                         PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
+       .hw_list        = &m4ulist,
+       .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .banks_num      = 1,
+       .banks_enable   = {true},
+       .iova_region    = mt8192_multi_dom,
+       .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+       .larbid_remap   = {{2}, {0}, {21}, {0}, {19}, {9, 10,
+                          11 /* 11a */, 25 /* 11c */},
+                          {13, 0, 29 /* 16b */, 30 /* 17b */, 0},

{5}},

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+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vpp = {
+       .m4u_plat       = M4U_MT8188,
+       .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS |

OUT_ORDER_WR_EN |

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+                         WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE

|

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+                         PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
+       .hw_list        = &m4ulist,
+       .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+       .banks_num      = 1,
+       .banks_enable   = {true},
+       .iova_region    = mt8192_multi_dom,
+       .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+       .larbid_remap   = {{1}, {3}, {23}, {7},

{MTK_INVALID_LARBID},

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+                          {12, 15, 24 /* 11b */}, {14,

MTK_INVALID_LARBID,

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+                          16 /* 16a */, 17 /* 17a */,

MTK_INVALID_LARBID,

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+                          27, 28 /* ccu0 */, MTK_INVALID_LARBID},

{4, 6}},

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+};
+
 static const unsigned int

mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] =
{

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        [0] = {~0, ~0},                         /* Region0: larb0/1

*/

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        [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},      /* Region1:

larb4/5/7 */

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@@ -1701,6 +1747,9 @@ static const struct of_device_id

mtk_iommu_of_ids[] = {

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        { .compatible = "mediatek,mt8173-m4u", .data =

&mt8173_data},

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        { .compatible = "mediatek,mt8183-m4u", .data =

&mt8183_data},

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        { .compatible = "mediatek,mt8186-iommu-mm",    .data =

&mt8186_data_mm}, /* mm: m4u */

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+       { .compatible = "mediatek,mt8188-iommu-infra", .data =

&mt8188_data_infra},

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+       { .compatible = "mediatek,mt8188-iommu-vdo",   .data =

&mt8188_data_vdo},

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+       { .compatible = "mediatek,mt8188-iommu-vpp",   .data =

&mt8188_data_vpp},

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        { .compatible = "mediatek,mt8192-m4u", .data =

&mt8192_data},

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        { .compatible = "mediatek,mt8195-iommu-infra", .data =

&mt8195_data_infra},

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        { .compatible = "mediatek,mt8195-iommu-vdo",   .data =

&mt8195_data_vdo},

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--
2.25.1