On 8.08.2023 07:14, Imran Shaik wrote:

From: Taniya Das <redacted>

Clock CBCRs with memories need an update for memory before enable/disable
of the clock. Add support for the mem ops to handle this sequence.

Signed-off-by: Taniya Das <redacted>
Signed-off-by: Imran Shaik <redacted>
---

Could you expand the commit message a bit? What does this clock
memory do?

[..]

+static int clk_branch2_mem_enable(struct clk_hw *hw)
+{
+	struct clk_branch *br = to_clk_branch(hw);
+	u32 val;
+	int count = 200;
+
+	regmap_update_bits(br->clkr.regmap, br->mem_enable_reg,
+			br->mem_enable_ack_bit, br->mem_enable_ack_bit);
+
+	regmap_read(br->clkr.regmap, br->mem_ack_reg, &val);
+
+	while (count-- > 0) {
+		if (val & br->mem_enable_ack_bit)
+			return clk_branch2_enable(hw);
+		udelay(1);
+		regmap_read(br->clkr.regmap, br->mem_ack_reg, &val);
+	}

readl_poll_timeout?

Konrad