Thread (90 messages) 90 messages, 7 authors, 2023-08-08

Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling

From: Manivannan Sadhasivam <hidden>
Date: 2023-07-28 02:51:32
Also in: linux-pci, linux-renesas-soc

On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
Hi Manivannan,
quoted
From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM

Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
handling".
I got it.
quoted
On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
quoted
Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
field there is another one which needs to be updated. It's
LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
the very least the maximum link-width capability CSR won't expose
the actual maximum capability.

[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.60a, March 2015, p.1032
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.70a, March 2016, p.1065
[3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    Version 4.90a, March 2016, p.1057
...
[X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
      Version 5.40a, March 2019, p.1396
[X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
      Version 5.40a, March 2019, p.1266

Suggested-by: Serge Semin <redacted>
Add Reported-by also?
I don't think so because Serge suggested the commit description from my submitted patch [1].

[1]
https://lore.kernel.org/linux-pci/20230322065701.po7owyzwisntalyz@mobilestation/ (local)
Fine then.
quoted
quoted
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This looks like a potential bug fix to me. So please move this change before the
previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
CC stable list for backporting.
I think that this patch should be a next branch because this is possible to
cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
without this setting.

Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
Additionally, I could not determine which old kernel versions should have this patch
applied as backporting.
Ok. But you can still move this patch as I suggested. If we happen to hit any
issue with this setting, then we can easily revert it.

- Mani
Best regards,
Yoshihiro Shimoda
quoted
- Mani
quoted
Reviewed-by: Serge Semin <redacted>
---
 drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 5cca34140d2a..c4998194fe74 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)

 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
 {
-	u32 lwsc, plc;
+	u32 lnkcap, lwsc, plc;
+	u8 cap;

 	if (!num_lanes)
 		return;
@@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
 	}
 	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
 	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+
+	cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
+	lnkcap &= ~PCI_EXP_LNKCAP_MLW;
+	lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
+	dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
 }

 void dw_pcie_iatu_detect(struct dw_pcie *pci)
--
2.25.1
--
மணிவண்ணன் சதாசிவம்
-- 
மணிவண்ணன் சதாசிவம்
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