Thread (1 message) 1 message, 1 author, 2023-07-19

[PATCH v10 2/4] arm: dts: qcom: sdx65: Add PCIe EP interconnect path

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From: Krishna chaitanya chundru <hidden>
Date: 2023-07-19 07:21:17
Also in: linux-arm-msm, linux-pci, lkml
Subsystem: arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers: Bjorn Andersson, Konrad Dybcio, Linus Torvalds

Revision v10 of 8 in this series; 1 review trailer; landed in mainline as 84d2ae7c09d9 on 2024-12-27.

Revisions (8)
  1. v3 [diff vs current]
  2. v4 [diff vs current]
  3. v5 [diff vs current]
  4. v6 [diff vs current]
  5. v7 [diff vs current]
  6. v8 [diff vs current]
  7. v9 [diff vs current]
  8. v10 current
Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform.

Reviewed-by: Manivannan Sadhasivam <redacted>
Signed-off-by: Krishna chaitanya chundru <redacted>
---
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 1a35830..69fe7e5 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -332,6 +332,10 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "global", "doorbell";
 
+			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>,
+					<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
 
-- 
2.7.4
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