Re: [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2023-07-10 14:21:40
Also in:
linux-gpio, linux-renesas-soc, linux-riscv, lkml
Hi Prabhakar, On Fri, Jun 30, 2023 at 2:05 PM Prabhakar [off-list ref] wrote:
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update the gpio-ranges property in RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
quoted hunk ↗ jump to hunk
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi@@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>;
Is that correct? You only have 32 more pins than on r9a07g043u,
which uses:
gpio-ranges = <&pinctrl 0 0 152>;
+};
+
&soc {
dma-noncoherent;
interrupt-parent = <&plic>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds