[PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110
From: Minda Chen <minda.chen@starfivetech.com>
Date: 2023-06-29 07:53:41
Also in:
linux-phy, linux-riscv, lkml
Subsystem:
risc-v architecture, starfive devicetrees, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Emil Renner Berthing, Conor Dooley, Linus Torvalds
Add PCIe PHY dts configuration for StarFive JH7110 SoC. PCIe0 PHY can be use as USB 3.0 PHY. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7e5c3ae83aa1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi@@ -353,6 +353,18 @@ status = "disabled"; }; + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>;
--
2.17.1