[PATCH 04/10] arm64: dts: imx8ulp: add cpuidle node
From: Peng Fan (OSS) <hidden>
Date: 2023-06-25 12:38:20
Also in:
linux-arm-kernel, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Peng Fan <peng.fan@nxp.com> Add cpuidle node and enable cpuidle for dual cores. The HW mode in Arm Trusted Firmware is SoC Application Power Domain Sleep mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index fd30475a561d..16906c20bce9 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi@@ -40,6 +40,7 @@ A35_0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_1: cpu@1 {
@@ -48,6 +49,7 @@ A35_1: cpu@1 { reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_L2: l2-cache0 {
@@ -55,6 +57,19 @@ A35_L2: l2-cache0 { cache-level = <2>; cache-unified; }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + }; + }; }; gic: interrupt-controller@2d400000 {
--
2.37.1