Re: [PATCH 13/15] arm64: dts: qcom: sm6125: Add dispcc node
From: Dmitry Baryshkov <hidden>
Date: 2023-06-24 13:52:41
Also in:
dri-devel, linux-arm-msm, linux-clk, lkml
On 24/06/2023 03:41, Marijn Suijten wrote:
quoted hunk ↗ jump to hunk
Enable and configure the dispcc node on SM6125 for consumption by MDSS later on. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index edb03508dba3..7d78b4e48ebe 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi@@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> */ +#include <dt-bindings/clock/qcom,dispcc-sm6125.h> #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/dma/qcom-gpi.h>@@ -1203,6 +1204,28 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,sm6125-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
This clock is at the wrong position.
+ clock-names = "bi_tcxo",
+ "gcc_disp_gpll0_div_clk_src",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ power-domains = <&rpmpd SM6125_VDDCX>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0c600000 0x80000>;-- With best wishes Dmitry