On Thu, Mar 23, 2023 at 2:10 AM Brad Larson [off-list ref] wrote:

Add support for AMD Pensando Elba SoC which explicitly
controls byte-lane enables on writes.

Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
IO memory accessors

+/* Elba control register bits [6:3] are byte-lane enables */
+#define ELBA_BYTE_ENABLE_MASK(x)       ((x) << 3)

+static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
+                            void __iomem *reg)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&priv->wrlock, flags);
+       writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);

GENMASK(3, 0) ?

+       writel(val, reg);
+       spin_unlock_irqrestore(&priv->wrlock, flags);
+}

...

+       byte_enables = GENMASK(1, 0) << (reg & 0x3);

   unsigned u32 shift = reg & GENMASK(1, 0);

   byte_enables = GENMASK(1, 0) << shift;

?

...

+       byte_enables = BIT(0) << (reg & 0x3);

In a similar way?

   unsigned u32 shift = reg & GENMASK(1, 0);

   byte_enables = BIT(0) << shift;

-- 
With Best Regards,
Andy Shevchenko