[PATCH v2 11/23] arm64: dts: Update cache properties for marvell
From: Pierre Gondois <pierre.gondois@arm.com>
Date: 2022-11-07 16:20:19
Also in:
linux-amlogic, linux-arm-msm, linux-mediatek, linux-renesas-soc, linux-samsung-soc, linux-tegra, lkml
Subsystem:
arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, the rest · Maintainers:
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Linus Torvalds
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
For ac5-98dx25xx.dtsi:
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4 ++++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 4 ++++
4 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 44ed6f963b75..7308f7b6b22c 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi@@ -49,6 +49,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..6713b2ee50c9 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi@@ -48,9 +48,11 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..695c8f070dbc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi@@ -78,16 +78,20 @@ cpu3: cpu@101 { l2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..878d82bb1052 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi@@ -78,16 +78,20 @@ cpu3: cpu@101 { l2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; };
--
2.25.1