Thread (32 messages) read the whole thread 32 messages, 2 authors, 2022-08-30
STALE1431d LANDED: 1 (0M)

Revision v4 of 4 in this series; 1 review trailer; landed in mainline as 55fc8c419b1f on 2022-08-30.

Revisions (4)
  1. v1 [diff vs current]
  2. v2 [diff vs current]
  3. v3 [diff vs current]
  4. v4 current

[PATCH v4 05/30] dt-bindings: phy: qcom,qmp: clean up descriptions

From: Johan Hovold <johan+linaro@kernel.org>
Date: 2022-08-30 11:30:12
Also in: linux-arm-msm, linux-phy, lkml
Subsystem: arm/qualcomm mailing list, generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds

Clean up the remaining descriptions by using uppercase "PHY"
consistently and dropping redundant information from the register
descriptions.

Acked-by: Krzysztof Kozlowski <redacted>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 370a7e55622f..d2b35562b9cb 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -11,7 +11,7 @@ maintainers:
   - Vinod Koul <vkoul@kernel.org>
 
 description:
-  QMP phy controller supports physical layer functionality for a number of
+  QMP PHY controller supports physical layer functionality for a number of
   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
 
 properties:
@@ -65,8 +65,8 @@ properties:
   reg:
     minItems: 1
     items:
-      - description: Address and length of PHY's common serdes block.
-      - description: Address and length of PHY's DP_COM control block.
+      - description: serdes
+      - description: DP_COM
 
   "#address-cells":
     enum: [ 1, 2 ]
-- 
2.35.1
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