Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding

On 15/07/2022 12:17, Biju Das wrote:

Hi Krzysztof Kozlowski,

Thanks for the feedback.

quoted

Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
binding

On 13/07/2022 15:55, Biju Das wrote:

quoted

Add device tree bindings for the RZ/G2L Port Output Enable for GPT

(POEG).

quoted

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
REF->v1:
 * Modelled as pincontrol as most of its configuration is intended to

be

quoted

   static.
 * Updated reg size in example.
---
 .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  | 65
+++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml

diff --git
a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
new file mode 100644
index 000000000000..7607dd87fa68

--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
+++ l

@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+
+title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+  The output pins of the general PWM timer (GPT) can be disabled by
+using
+  the port output enabling function for the GPT (POEG). Specifically,
+  either of the following ways can be used.
+  * Input level detection of the GTETRGA to GTETRGD pins.
+  * Output-disable request from the GPT.

Shouldn't this all be part of GPT? Is this a real separate device in the
SoC?

No, It is separate IP block, having its own register block, interrupts and resets.

Please see RFC discussion here[1]

[1] https://lore.kernel.org/linux-renesas-soc/20220517210407.GA1635524-robh@kernel.org/ (local)

quoted

quoted

+  * Register settings.

This is confusing... so you can use POEG to mess up registers of GPT
independently, so GPT does not know it?

POEG does not mess up registers of GPT. It is basically for protection.

Using POEG register, it is possible to disable GPT output without the knowledge of GPT, after configuring the Output disable source select in the GTINTAD (General PWM Timer Interrupt Output Setting Register) register present in GPT.

Then what does it mean:
"...following ways can be used. Register settings."
I cannot parse it.


Best regards,
Krzysztof