Re: [PATCH v5 2/4] arm64: dts: mt8192: Add mmc device nodes

On 31/03/2022 14:48, allen-kh.cheng wrote:

Hi Matthias,

On Thu, 2022-03-31 at 14:02 +0200, Matthias Brugger wrote:

quoted

On 30/03/2022 15:38, Allen-KH Cheng wrote:

quoted

Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <redacted>
Reviewed-by: AngeloGioacchino Del Regno <
angelogioacchino.delregno@collabora.com>

You forgot to disable the msdc clock node, which I understood we
agreed on in in
v4. I would consider this change as an substantial one, so in this
case please
delete the reviewed-by tags.

Regards,
Matthias

Is it ok I send a new patch for this instead of a series?

Yes sure.

Matthias

Best regards,
Allen

quoted

quoted

---
   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 32
++++++++++++++++++++++++
   1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi

b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69e8d1934d53..c1057878e2c6 100644

--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi

@@ -991,6 +991,38 @@
   			#clock-cells = <1>;
   		};
   
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc",

"mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top
CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg",
"sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc",
"mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0
0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top
CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg",
"sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
   		mfgcfg: clock-controller@13fbf000 {
   			compatible = "mediatek,mt8192-mfgcfg";
   			reg = <0 0x13fbf000 0 0x1000>;