[PATCH 5/8] dma: dw: Avoid partial transfers
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2022-02-18 18:12:46
Also in:
dmaengine, linux-clk, linux-renesas-soc
Subsystem:
dma generic offload engine subsystem, synopsys designware dmac driver, the rest · Maintainers:
Vinod Koul, Viresh Kumar, Linus Torvalds
From: Phil Edworthy <redacted> Pausing a partial transfer only causes data to be written to mem that is a multiple of the memory width setting. However, when a DMA client driver finishes DMA early, e.g. due to UART char timeout interrupt, all data read from the DEV must be written to MEM. Therefore, allow the slave to limit the memory width to ensure all data read from the DEV is written to MEM when DMA is paused. Signed-off-by: Phil Edworthy <redacted> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/dma/dw/core.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 7ab83fe601ed..48cdefe997f1 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c@@ -705,6 +705,9 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : DWC_CTLL_FC(DW_DMA_FC_D_P2M); + if (sconfig->dst_addr_width && sconfig->dst_addr_width < data_width) + data_width = sconfig->dst_addr_width; + for_each_sg(sgl, sg, sg_len, i) { struct dw_desc *desc; u32 len, mem;
--
2.27.0