[PATCH v3 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2021-12-17 12:49:50
Also in:
linux-riscv
Subsystem:
risc-v architecture, risc-v microchip support, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Daire McNamara, Linus Torvalds
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <redacted> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> --- v3: - Add Tested-by, v2: - Add Reviewed-by. --- .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi@@ -158,18 +158,18 @@ cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 {
@@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; riscv,ndev = <186>; };
@@ -190,7 +190,8 @@ dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; };
@@ -254,7 +255,7 @@ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88 89>; + interrupts = <88>, <89>; clocks = <&clkcfg 6>; max-frequency = <200000000>; status = "disabled";
@@ -264,7 +265,7 @@ emac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; + interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 4>, <&clkcfg 2>; clock-names = "pclk", "hclk";
@@ -277,7 +278,7 @@ emac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; + interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 5>, <&clkcfg 2>; status = "disabled";
--
2.25.1