Hi Reinhold,
On Mon, Dec 20, 2021 at 4:23 AM [off-list ref] wrote:
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1-cs {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
This version looks good to me.
One nit: you seem to use a single SPI chipselect, but you add two entries here.
Is the MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 needed too?
Either way:
Reviewed-by: Fabio Estevam <festevam@gmail.com>