-----Original Message-----
From: Vinod Koul <vkoul@kernel.org>
Sent: Thursday, December 2, 2021 2:03 PM
To: Hongxing Zhu <hongxing.zhu@nxp.com>
Cc: Lorenzo Pieralisi <redacted>;
l.stach@pengutronix.de; bhelgaas@google.com; Marcel Ziswiler
[off-list ref]; tharvey@gateworks.com;
kishon@ti.com; robh@kernel.org; galak@kernel.crashing.org;
shawnguo@kernel.org; linux-phy@lists.infradead.org;
devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
kernel@pengutronix.de; dl-linux-imx [off-list ref]
Subject: Re: [PATCH v6 0/8] Add the imx8m pcie phy driver and imx8mm
pcie support

On 02-12-21, 05:43, Hongxing Zhu wrote:

quoted

quoted

-----Original Message-----
From: Lorenzo Pieralisi <redacted>
Sent: Wednesday, December 1, 2021 8:44 PM
To: Hongxing Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de; bhelgaas@google.com; Marcel Ziswiler
[off-list ref]; tharvey@gateworks.com;

kishon@ti.com;

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vkoul@kernel.org; robh@kernel.org; galak@kernel.crashing.org;
shawnguo@kernel.org; linux-phy@lists.infradead.org;
devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
linux-arm-kernel@lists.infradead.org;
linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
[off-list ref]
Subject: Re: [PATCH v6 0/8] Add the imx8m pcie phy driver and

imx8mm

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pcie support

On Thu, Nov 18, 2021 at 09:54:41AM +0800, Richard Zhu wrote:

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Refer to the discussion [1] when try to enable i.MX8MM PCIe
support, one standalone PCIe PHY driver should be seperated from
i.MX PCIe driver when enable i.MX8MM PCIe support.

This patch-set adds the standalone PCIe PHY driver suport[1-5],
and i.MX8MM PCIe support[6-8] to have whole view to review this

patch-set.

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The PCIe works on i.MX8MM EVK board based the the blkctrl power

driver

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[2] and this patch-set. And tested by Tim and Marcel on the
different reference clock modes boards.

[1]

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa

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tc

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hwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F20210510141509.

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929120

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-3-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongxing.zhu

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%40nxp.c

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AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&

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amp;sdata=

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5xlZSnBYs1SIIbMnmlQwi0qtfLDgKbueLNjPWIPD1pw%3D&reserved=

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0

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[2]

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa

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tc

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hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F20210910

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202640

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.980366-1-l.stach%40pengutronix.de%2F&data=04%7C01%7C

hon

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gxing.zhu%

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7C3000&amp

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Main changes v5 --> v6:
- Add "Reviewed-by: Rob Herring [off-list ref]" into #1 and

#3

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patches.

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- Merge Rob's review comments to the #2 patch.

Main changes v4 --> v5:
- Set the AUX_EN always 1b'1, thus it can fix the regression
introduced

in v4

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  series on Marcel's board.
- Use the lower-case letter in the devicetreee refer to Marcel's

comments.

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_ Since the default value of the deemphasis parameters are zero,
only

set

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  the deemphasis registers when the input paramters are none

zero.

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Main changes v3 --> v4:
- Update the yaml to fix syntax error, add maxitems and drop
description of phy
- Correct the clock name in PHY DT node.
- Squash the EVK board relalted dts changes into one patch, and
drop

the

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  useless dummy clock and gpio suffix in DT nodes.
- Add board specific de-emphasis parameters as DT properties. Thus

each board

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  can specify its actual de-emphasis values.
- Update the commit log of PHY driver.
- Remove the useless codes from PCIe driver, since they are moved
to PHY driver
- After the discussion and verification of the CLKREQ#
configurations

with Tim,

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  agree to add an optional boolean property
"fsl,clkreq-unsupported",

indicates

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  the CLKREQ# signal is hooked or not in HW designs.
- Add "Tested-by: Marcel Ziswiler [off-list ref]"
tag,

since

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  Marcel help to test the v3 patch-set.

Main changes v2 --> v3:
- Regarding Lucas' comments.
 - to have a whole view to review the patches, send out the
i.MX8MM

PCIe support too.

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 - move the PHY related bits manipulations of the GPR/SRC to

standalone PHY driver.

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 - split the dts changes to SOC and board DT, and use the enum
instead

of raw value.

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 - update the license of the dt-binding header file.

Changes v1 --> v2:
- Update the license of the dt-binding header file to make the

license

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  compatible with dts files.
- Fix the dt_binding_check errors.

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml    |

6

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+++

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Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |

92

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+++++++++++++++++++++++++++++++

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arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

|

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55 +++++++++++++++++++

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arch/arm64/boot/dts/freescale/imx8mm.dtsi

|

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46 +++++++++++++++-

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drivers/pci/controller/dwc/pci-imx6.c

|

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73 ++++++++++++++++++++++---

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drivers/phy/freescale/Kconfig

|

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9 ++++

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drivers/phy/freescale/Makefile

|

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1 +

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drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   |

237

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

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+++++++++++++++++++++

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include/dt-bindings/phy/phy-imx8-pcie.h

|

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14 +++++

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9 files changed, 525 insertions(+), 8 deletions(-)

Hi Richard,

I can pull this series into the PCI tree (but not the dts changes
that should be routed elsewhere) or give an ACK for patch 8, please
let me know what's the best option.

[Richard Zhu] Hi Lorenzo:
First of all, thanks a lot for your kindly help.
To my original understand, #1-3 patch had been reviewed by Rob, might
be  merged into Rob's dt-binding git repos.
Shawn takes dts changes ( #4, #6 and #7). And PHY driver merged by
vkoul  or Kishon.
In the end, the PCIe changes(#8) are merged into PCIe git repos.

I'm appreciated if you pull this whole series although I'm not sure
that  you can do it or not.
Today, I'm glad to receive vkoul's comments about the PHY driver part.
Let me continue refine the PHY driver, send anther version of this

patch-set.

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Then, let's figure out what's the best option to merge this series.

I think phy binding and driver changes should go thru phy tree and pcie
binding and driver changes thru pcie tree, dt should be picked by
respective arch tree

[Richard Zhu] Hi Vinod: I'm fine with this option.
Please help to take the phy binding and driver after the review cycle.
Thanks in advanced.

Best regards
Richard

--
~Vinod