Re: [PATCH 2/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi"
From: Rob Herring <robh@kernel.org>
Date: 2021-11-30 21:01:37
Also in:
linux-spi
On Mon, Nov 22, 2021 at 10:04:27AM -0600, Dinh Nguyen wrote:
quoted hunk ↗ jump to hunk
The QSPI controller on Intel's SoCFPGA platform does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash. Introduce the dts binding "intel,socfpga-qspi" to differentiate the hardware. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + 1 file changed, 1 insertion(+)diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index ca155abbda7a..037f41f58503 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml@@ -29,6 +29,7 @@ properties: - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi - const: cdns,qspi-nor
Doesn't match what you changed in the dts files. Please run schema validation so YOU find this issue and typos instead of me. Rob