diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index 80c10a0..3185a5a 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -42,6 +42,9 @@ const struct ath11k_bus_params ath11k_hybrid_bus_params = {
.fixed_bdf_addr = false,
.fixed_mem_region = false,
.hybrid_bus_type = true,
+ .static_window_map = true,
+ .dp_window_idx = 1,
+ .ce_window_idx = 2,
};
#define ATH11K_IRQ_CE0_OFFSET 4diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index f07fff9..a4b56df 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -639,6 +639,8 @@ struct ath11k_bus_params {
bool fixed_mem_region;
bool static_window_map;
bool hybrid_bus_type;
+ u8 dp_window_idx;
+ u8 ce_window_idx;
struct {
void (*wakeup)(struct ath11k_base *ab);
void (*release)(struct ath11k_base *ab);diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index d85894e..b473c5e 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -755,6 +755,10 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ab->bus_params.ops.wakeup = NULL;
ab->bus_params.ops.release = NULL;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
+
+ /* For QCN9074, CE: 2nd window, UMAC: 3rd window */
+ ab->bus_params.ce_window_idx = 2;
+ ab->bus_params.dp_window_idx = 3;
break;
case WCN6855_DEVICE_ID:
ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
diff --git a/drivers/net/wireless/ath/ath11k/pci_cmn.c b/drivers/net/wireless/ath/ath11k/pci_cmn.c
index 9aad314..76db5a6 100644
--- a/drivers/net/wireless/ath/ath11k/pci_cmn.c
+++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
@@ -122,16 +122,13 @@ int ath11k_pci_get_msi_config(struct ath11k_base *ab)
static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
u32 offset)
{
- u32 window_start;
+ u32 window_start = 0;
- /* If offset lies within DP register range, use 3rd window */
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 3 * ATH11K_PCI_WINDOW_START;
- /* If offset lies within CE register range, use 2nd window */
- else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK)
- window_start = 2 * ATH11K_PCI_WINDOW_START;
- else
- window_start = ATH11K_PCI_WINDOW_START;
+ window_start = ab->bus_params.dp_window_idx * ATH11K_PCI_WINDOW_START;
+ else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
+ ATH11K_PCI_WINDOW_RANGE_MASK)
+ window_start = ab->bus_params.ce_window_idx * ATH11K_PCI_WINDOW_START;
return window_start;
}@@ -151,17 +148,12 @@ void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
if (offset < ATH11K_PCI_WINDOW_START) {
iowrite32(value, ab->mem + offset);
} else {
- if (ab->bus_params.static_window_map)
+ if (ab->bus_params.static_window_map) {
window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START &&
- ab->bus_params.ops.window_write32) {
- ab->bus_params.ops.window_write32(ab, offset, value);
- } else {
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ } else if (ab->bus_params.ops.window_write32) {
+ ab->bus_params.ops.window_write32(ab, offset, value);
}
}
@@ -186,17 +178,12 @@ u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
if (offset < ATH11K_PCI_WINDOW_START) {
val = ioread32(ab->mem + offset);
} else {
- if (ab->bus_params.static_window_map)
+ if (ab->bus_params.static_window_map) {
window_start = ath11k_pci_get_window_start(ab, offset);
- else
- window_start = ATH11K_PCI_WINDOW_START;
-
- if (window_start == ATH11K_PCI_WINDOW_START &&
- ab->bus_params.ops.window_read32) {
- val = ab->bus_params.ops.window_read32(ab, offset);
- } else {
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
+ } else if (ab->bus_params.ops.window_read32) {
+ val = ab->bus_params.ops.window_read32(ab, offset);
}
}
--
2.7.4