Hi Guenter,

On Wed, 2021-11-17 at 04:42 -0800, Guenter Roeck wrote:

On 11/16/21 11:13 PM, Sander Vanheule wrote:

quoted

Hi Guenter,

On Tue, 2021-11-16 at 21:20 -0800, Guenter Roeck wrote:

quoted

On Thu, Nov 04, 2021 at 10:32:13AM +0100, Sander Vanheule wrote:

quoted

Realtek MIPS SoCs (platform name Otto) have a watchdog timer with
pretimeout notifitication support. The WDT can (partially) hard reset,
or soft reset the SoC.

This driver implements all features as described in the devicetree
binding, except the phase2 interrupt, and also functions as a restart
handler. The cpu reset mode is considered to be a "warm" restart, since
this mode does not reset all peripherals. Being an embedded system
though, the "cpu" and "software" modes will still cause the bootloader
to run on restart.

It is not known how a forced system reset can be disabled on the
supported platforms. This means that the phase2 interrupt will only fire
at the same time as reset, so implementing phase2 is of little use.

Signed-off-by: Sander Vanheule <sander@svanheule.net>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

Thank you for the review! In the meantime, I was preparing a v4 of this series with some
small changes (see inline below). Could you let me know if I can keep your Reviewed-by
with those changes?

I think it would be better to re-review it.

I sent out the v4 a bit later than expected, because I hit a regression for the irqchip on
this platform:
https://lore.kernel.org/all/bbe5506a2458b2d6049bd22a5fda77ae6175ddec.camel@svanheule.net/ (local)


Best,
Sander