Re: [RFC PATCH v3 0/7] Renesas RZ/G2L IRQC support
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: 2021-11-12 14:23:01
Also in:
linux-gpio, linux-renesas-soc, lkml
Hi Geert, On Fri, Nov 12, 2021 at 2:12 PM Geert Uytterhoeven [off-list ref] wrote:
Hi Prabhakar, On Wed, Nov 10, 2021 at 11:58 PM Lad Prabhakar [off-list ref] wrote:quoted
The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's with below pins: - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a maximum of only 32 can be mapped to 32 GIC SPI interrupts, - NMI edge select. _____________ | GIC | | ________ | ____________ | | | | NMI ------------------------------------>| | SPI0-479 | | GIC-600| | _______ | |------------>| | | | | | | PPI16-31 | | | | | | IRQ0-IRQ8 | IRQC |------------>| | |IRQ0-IRQ7?
oops typo here.
quoted
P0_P48_4 ------>| GPIO |---------------->| | | |________| | | |GPIOINT0-122 | | | | | |---------------->| TINT0-31 | | | |______| |__________| |____________| The proposed RFC patches, add the IRQ domains in GPIO (pinctrl driver) and the IRQC driver. The IRQC domain handles the actual SPI interrupt and upon reception of the interrupt it propagates to the GPIO IRQ domain to handle virq.
Also this bit isnt true (copy pasted from v1 :(). IRQ now is handled by the slave driver requesting interrupts. IRQC now handles eoi callbacks.
quoted
Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is handled by the IRQC driver.
Cheers, Prabhakar
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
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when I'm talking to journalists I just say "programmer" or something like that.
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