Hi Wolfram,

Thank you for the review.

On Tue, Nov 2, 2021 at 11:48 AM Wolfram Sang
[off-list ref] wrote:

Hi Prabhakar,

quoted

+#define RPCIF_PHYADD         0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
+#define RPCIF_PHYWR          0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */

Nice detailed research, thanks! Minor nit: Keep the sorting
alphabetical: D3, E3, V3M.

quoted

+static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
+{
+     u32 data;
+
+     regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
+     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
+     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
+     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
+     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
+     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
+
+     regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
+     regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
+     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
+     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
+}

Still magic values here. Don't you have them explained in your Gen3
documentation? It is tables 62.16 and 62.17 in my versions.

Oops I missed that, does the below look good?

#define RPCIF_PHYADD_ADD_MD 0x00
#define RPCIF_PHYADD_ADD_RDLSEL 0x22
#define RPCIF_PHYADD_ADD_FDLSEL 0x24
#define RPCIF_PHYADD_ADD_RDLMON 0x26
#define RPCIF_PHYADD_ADD_FDLMON 0x28

#define RPCIF_PHYADD_ACCEN BIT(31)
#define RPCIF_PHYADD_RW BIT(30)
#define RPCIF_PHYADD_ADD(v) (v & 0x3f)

#define RPCIF_MD_PHYREGEN_VAL 0xa539
#define RPCIF_MD_PHYREGEN(v) ((v & 0xffff) << 16)

#define RPCIF_RDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_RDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_RDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_RDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

#define RPCIF_FDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_FDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_FDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_FDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

+     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
+     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);

For the above do you have any suggestions? As I couldn't find any
details about it or shall I just go with magic numbers for now?

Other than these, looks good.

thanks, once we agree upon above I shall re-spin v3.

Cheers,
Prabhakar

Thanks,

   Wolfram