[PATCH v3 1/7] dt-bindings: clock: Add MT8192 APU clock bindings
From: Flora Fu <hidden>
Date: 2021-10-23 10:13:52
Also in:
linux-arm-kernel, linux-clk, linux-mediatek, lkml
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add clock bindings for APU on MT8192. Signed-off-by: Flora Fu <redacted> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> --- include/dt-bindings/clock/mt8192-clk.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h
index 5ab68f15a256..d5ac7b6c1d5c 100644
--- a/include/dt-bindings/clock/mt8192-clk.h
+++ b/include/dt-bindings/clock/mt8192-clk.h@@ -164,7 +164,15 @@ #define CLK_TOP_APLL12_DIV9 152 #define CLK_TOP_SSUSB_TOP_REF 153 #define CLK_TOP_SSUSB_PHY_REF 154 -#define CLK_TOP_NR_CLK 155 +#define CLK_TOP_DSP_SEL 155 +#define CLK_TOP_DSP1_SEL 156 +#define CLK_TOP_DSP1_NPUPLL_SEL 157 +#define CLK_TOP_DSP2_SEL 158 +#define CLK_TOP_DSP2_NPUPLL_SEL 159 +#define CLK_TOP_DSP5_SEL 160 +#define CLK_TOP_DSP5_APUPLL_SEL 161 +#define CLK_TOP_IPU_IF_SEL 162 +#define CLK_TOP_NR_CLK 163 /* INFRACFG */
@@ -309,7 +317,9 @@ #define CLK_APMIXED_APLL1 8 #define CLK_APMIXED_APLL2 9 #define CLK_APMIXED_MIPID26M 10 -#define CLK_APMIXED_NR_CLK 11 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_NPUPLL 12 +#define CLK_APMIXED_NR_CLK 13 /* SCP_ADSP */
--
2.18.0