[PATCH 07/11] arm64: dts: qcom: sm6350: add debug uart
From: Luca Weiss <hidden>
Date: 2021-10-03 08:33:32
Also in:
linux-arm-msm, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
Add the necessary nodes for the debug uart on SM6350. Signed-off-by: Luca Weiss <redacted> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 95e69d9f8657..630a76e740f8 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi@@ -445,6 +445,30 @@ opp-384000000 { }; }; + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x4c3 0x0>; + ranges; + status = "disabled"; + + uart2: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x98c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -672,6 +696,13 @@ tlmm: pinctrl@f100000 { interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + + qup_uart2_default: qup-uart2-default { + mux { + pins = "gpio25", "gpio26"; + function = "qup13_f2"; + }; + }; }; apps_smmu: iommu@15000000 {
--
2.33.0