From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-08-17 09:03:34
This patch series aims to document RZ/G2L SDHI controller bindings.
v3->v4:
* Removed duplicate clock-names for sdhi-r7sxxxx SoC's
* Defined clock-names for RZ/G2L SoC and made this as required property.
v2->v3:
* Created a separate patch to fix the dtbs-warning check reported by [1].
* RZ/G2L SDHI binding patch depends up on the above the patch.
[1] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210804091940.23983-1-biju.das.jz@bp.renesas.com/
v1->v2:
* Fixed dtbs-check issue for RZ/A{1,2} platforms.
v1->
* newpatch
Biju Das (2):
dt-bindings: mmc: renesas,sdhi: Fix dtbs-check warning
dt-bindings: mmc: renesas,sdhi: Document RZ/G2L bindings
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 133 ++++++++++++------
1 file changed, 89 insertions(+), 44 deletions(-)
--
2.17.1
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-08-17 09:03:36
Document RZ/G2L SDHI controller bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* Defined clock-names for RZ/G2L SoC and make it as a required property
v2->v3:
* split the patch into 2, first one for fixing dtbs-check issue and
later one for documenting RZ/G2L SDHI bindings.
v1->v2:
* Fixed dtbs-check issue for RZ/A{1,2} platforms.
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 73 +++++++++++++------
1 file changed, 52 insertions(+), 21 deletions(-)
@@ -108,6 +103,42 @@ properties:allOf:-$ref:"mmc-controller.yaml"+-if:+properties:+compatible:+contains:+const:renesas,sdhi-r9a07g044+then:+properties:+clocks:+items:+-description:IMCLK, SDHI channel main clock1.+-description:IMCLK2, SDHI channel main clock2. When this clock is+turned off, external SD card detection cannot be+detected.+-description:CLK_HS, SDHI channel High speed clock which operates+4 times that of SDHI channel main clock1.+-description:ACLK, SDHI channel bus clock.+clock-names:+items:+-const:imclk+-const:imclk2+-const:clk_hs+-const:aclk+required:+-clock-names+-resets+else:+properties:+clocks:+minItems:1+maxItems:2+clock-names:+minItems:1+items:+-const:core+-const:cd+-if:properties:compatible:
@@ -104,14 +101,46 @@ properties:pinctrl-1:maxItems:1-pinctrl-names:-minItems:1-items:--const:default--const:state_uhs+pinctrl-names:truemax-frequency:true+allOf:+-$ref:"mmc-controller.yaml"++-if:+properties:+compatible:+contains:+const:renesas,sdhi-mmc-r8a77470+then:+properties:+pinctrl-names:+items:+-const:state_uhs+else:+properties:+pinctrl-names:+minItems:1+items:+-const:default+-const:state_uhs++-if:+properties:+compatible:+contains:+enum:+-renesas,sdhi-r7s72100+-renesas,sdhi-r7s9210+then:+required:+-clock-names+description:+The internal card detection logic that exists in these controllers is+sectioned off to be run by a separate second clock source to allow+the main core clock to be turned off to save power.+required:-compatible-reg
@@ -119,21 +148,6 @@ required:-clocks-power-domains-if:-properties:-compatible:-contains:-enum:--renesas,sdhi-r7s72100--renesas,sdhi-r7s9210-then:-required:--clock-names-description:-The internal card detection logic that exists in these controllers is-sectioned off to be run by a separate second clock source to allow-the main core clock to be turned off to save power.-unevaluatedProperties:falseexamples:
From: Rob Herring <robh@kernel.org> Date: 2021-08-18 14:22:14
On Tue, 17 Aug 2021 10:03:13 +0100, Biju Das wrote:
Document RZ/G2L SDHI controller bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* Defined clock-names for RZ/G2L SoC and make it as a required property
v2->v3:
* split the patch into 2, first one for fixing dtbs-check issue and
later one for documenting RZ/G2L SDHI bindings.
v1->v2:
* Fixed dtbs-check issue for RZ/A{1,2} platforms.
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 73 +++++++++++++------
1 file changed, 52 insertions(+), 21 deletions(-)
@@ -104,14 +101,46 @@ properties:pinctrl-1:maxItems:1-pinctrl-names:-minItems:1-items:--const:default--const:state_uhs+pinctrl-names:truemax-frequency:true+allOf:+-$ref:"mmc-controller.yaml"++-if:+properties:+compatible:+contains:+const:renesas,sdhi-mmc-r8a77470+then:+properties:+pinctrl-names:+items:+-const:state_uhs+else:+properties:+pinctrl-names:+minItems:1+items:+-const:default+-const:state_uhs++-if:+properties:+compatible:+contains:+enum:+-renesas,sdhi-r7s72100+-renesas,sdhi-r7s9210+then:+required:+-clock-names+description:+The internal card detection logic that exists in these controllers is+sectioned off to be run by a separate second clock source to allow+the main core clock to be turned off to save power.+required:-compatible-reg
@@ -119,21 +148,6 @@ required:-clocks-power-domains-if:-properties:-compatible:-contains:-enum:--renesas,sdhi-r7s72100--renesas,sdhi-r7s9210-then:-required:--clock-names-description:-The internal card detection logic that exists in these controllers is-sectioned off to be run by a separate second clock source to allow-the main core clock to be turned off to save power.-unevaluatedProperties:falseexamples:--
---
v3->v4:
* Defined clock-names for RZ/G2L SoC and make it as a required property
v2->v3:
* split the patch into 2, first one for fixing dtbs-check issue and
later one for documenting RZ/G2L SDHI bindings.
v1->v2:
* Fixed dtbs-check issue for RZ/A{1,2} platforms.
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 73 +++++++++++++------
1 file changed, 52 insertions(+), 21 deletions(-)
@@ -108,6 +103,42 @@ properties:allOf:-$ref:"mmc-controller.yaml"+-if:+properties:+compatible:+contains:+const:renesas,sdhi-r9a07g044+then:+properties:+clocks:+items:+-description:IMCLK, SDHI channel main clock1.+-description:IMCLK2, SDHI channel main clock2. When this clock is+turned off, external SD card detection cannot be+detected.+-description:CLK_HS, SDHI channel High speed clock which operates+4 times that of SDHI channel main clock1.+-description:ACLK, SDHI channel bus clock.+clock-names:+items:+-const:imclk+-const:imclk2+-const:clk_hs+-const:aclk+required:+-clock-names+-resets+else:+properties:+clocks:+minItems:1+maxItems:2+clock-names:+minItems:1+items:+-const:core+-const:cd+-if:properties:compatible:--
... as the clock handling is completely different.
Does this actually work with the current Linux SDHI driver? How are
the extra clocks handled?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-11-12 11:51:23
Hi Geert,
Subject: Re: [PATCH v4 2/2] dt-bindings: mmc: renesas,sdhi: Document
RZ/G2L bindings
Hi Biju,
On Tue, Aug 17, 2021 at 11:03 AM Biju Das [off-list ref]
wrote:
I don't think SDHI on RZ/G2L is fully compatible with SDHI on R-Car
Gen3...
It is is same IP, it has 2 main clk(core clocks), 1 high speed clock and 1 bus clock.
Core clocks are same running at 133MHz, High speed clock is at 533 MHz(133 x4) and bus clock
At 200MHz.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
m68k.org
In personal conversations with technical people, I call myself a hacker.
But when I'm talking to journalists I just say "programmer" or something
like that.
-- Linus Torvalds
From: Wolfram Sang <wsa+renesas@sang-engineering.com> Date: 2021-11-12 11:56:30
Hi everyone,
quoted
+ - description: IMCLK, SDHI channel main clock1.
Sounds like "core"
quoted
+ - description: IMCLK2, SDHI channel main clock2. When this clock is+ turned off, external SD card detection cannot be+ detected.
"cd"
quoted
+ - description: CLK_HS, SDHI channel High speed clock which operates
+ 4 times that of SDHI channel main clock1.
"clkh" compared to the Gen3 bindings to me.
quoted
+ - description: ACLK, SDHI channel bus clock.
This I don't understand. The CPG-MSSR clock?
Does this actually work with the current Linux SDHI driver? How are
the extra clocks handled?
It may work out of the box if their HW can have "clkh" enabled all the
time and this is their default. Gen3 has recommendations to disable clkh
for slow transfer modes, so we need handling of clkh
Kind regards,
Wolfram
Hi Wolfram,
On Fri, Nov 12, 2021 at 12:56 PM Wolfram Sang
[off-list ref] wrote:
quoted
quoted
+ - description: IMCLK, SDHI channel main clock1.
Sounds like "core"
quoted
quoted
+ - description: IMCLK2, SDHI channel main clock2. When this clock is+ turned off, external SD card detection cannot be+ detected.
"cd"
quoted
quoted
+ - description: CLK_HS, SDHI channel High speed clock which operates
+ 4 times that of SDHI channel main clock1.
"clkh" compared to the Gen3 bindings to me.
quoted
quoted
+ - description: ACLK, SDHI channel bus clock.
This I don't understand. The CPG-MSSR clock?
RZ/G2L has more fine-grained control of module clocks.
On e.g. R-Car SoCs, there is a single "MSTP" bit to disable "the"
module clock, but in practice it may control multiple clock inputs
to a module. The actual clock tree is not documented, so we model
this as a single module clock. So probably the MSTP bit controls
both the main channel clock and the bus clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds