[RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support
From: Anup Patel <hidden>
Date: 2021-08-30 04:18:33
Also in:
linux-riscv, lkml
Subsystem:
clocksource, clockevent drivers, open firmware and flattened device tree bindings, risc-v architecture, risc-v microchip support, risc-v misc soc support, the rest · Maintainers:
Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Daire McNamara, Linus Torvalds
The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means we have to create a IPI interrupt domain to use CLINT IPI functionality hence requiring a "interrupt-controller" and "#interrupt-cells" DT property in CLINT DT nodes. Impact of this CLINT DT bindings change only affects Linux RISC-V NoMMU kernel and has no effect of existing M-mode runtime firmwares (i.e. OpenSBI). Signed-off-by: Anup Patel <redacted> --- .../bindings/timer/sifive,clint.yaml | 20 ++++++++++++++----- arch/riscv/boot/dts/canaan/k210.dtsi | 2 ++ .../boot/dts/microchip/microchip-mpfs.dtsi | 2 ++ 3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index a35952f48742..9c8ef9f4094f 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml@@ -43,6 +43,12 @@ properties: interrupts-extended: minItems: 1 + maxItems: 4095 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true additionalProperties: false
@@ -50,15 +56,19 @@ required: - compatible - reg - interrupts-extended + - interrupt-controller + - "#interrupt-cells" examples: - | timer@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 - &cpu2intc 3 &cpu2intc 7 - &cpu3intc 3 &cpu3intc 7 - &cpu4intc 3 &cpu4intc 7>; - reg = <0x2000000 0x10000>; + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, + <&cpu2intc 3>, <&cpu2intc 7>, + <&cpu3intc 3>, <&cpu3intc 7>, + <&cpu4intc 3>, <&cpu4intc 7>; + reg = <0x2000000 0x10000>; + interrupt-controller; + #interrupt-cells = <0>; }; ...
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482..67dcda1efadb 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi@@ -105,6 +105,8 @@ clint0: timer@2000000 { reg = <0x2000000 0xC000>; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>; + #interrupt-cells = <0>; + interrupt-controller; }; plic0: interrupt-controller@c000000 {
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..67fb41439f20 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi@@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; + #interrupt-cells = <0>; + interrupt-controller; }; plic: interrupt-controller@c000000 {
--
2.25.1