Thread (19 messages) 19 messages, 4 authors, 2021-09-08

Re: [PATCH 1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings

From: Rob Herring <robh@kernel.org>
Date: 2021-08-24 14:34:35
Also in: linux-mmc, linux-riscv, lkml

On Thu, 19 Aug 2021 17:44:31 +0200, Krzysztof Kozlowski wrote:
All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
    ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
    Additional items are not allowed ('riscv' was unexpected)
    Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
    'riscv' was expected

Signed-off-by: Krzysztof Kozlowski <redacted>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
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