On Wed, 23 Jun 2021 13:59:26 +0200, Alex Bee wrote:

As can be seen in RK3328's TRM the register range for the GPU is
0xff300000 to 0xff330000.
It would (and does in vendor kernel) overlap with the registers of
the HEVC encoder (node/driver do not exist yet in upstream kernel).
See already existing h265e_mmu node.

Applied, thanks!

[1/1] arm64: dts: rockchip: Fix GPU register width for RK3328
      commit: 3f1c9b99f22c4784bd6f439a63bbf8a61c0335b1

Best regards,
-- 
Heiko Stuebner [off-list ref]