On Thu, 29 Jul 2021 23:34:42 +0530, Sibi Sankar wrote:

Re-arranging the register regions to support per core L3 DCVS would lead
to bindings breakage when using an older dt with a newer kernel. So,
document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
CPUFreq-hw driver to prevent such breakages.

Signed-off-by: Sibi Sankar <redacted>
---
 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>